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Mips Technologies R4000 - Data Transfer Rates

Mips Technologies R4000
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Chapter 12
350 MIPS R4000 Microprocessor User's Manual
Figure 12-34 shows an external intervention request to a cache line found
in the shared state, with the System interface initially in a master state.
Figure 12-35 shows an external intervention request to a cache line found
in the dirty exclusive state, with the System interface initially in a slave
state.
NOTE: Timings for the SysADC and SysCmdP buses are the same as
those of the SysAD and SysCmd buses, respectively.
Figure 12-34 External Intervention Request, Shared Line, System Interface in Master State
SCycle
1 2 3 4 5 6 7 8 9 10 11 12
SClock
SysAD Bus
Addr Unsd
SysCmd Bus
Ivtn CEOD
ValidOut*
ValidIn*
ExtRqst*
Release*
5
6
1
2
4
Master
Slave
Master
3

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