MIPS R4000 Microprocessor User's Manual F-1
Coprocessor 0 Hazards
F
The contents of the System Coprocessor registers and the TLB affect the
operation of the processor in many ways. For instance, an instruction that
changes CP0 data also affects subsequent instructions that use the data.
In the CPU, general registers are interlocked and the result of an
instruction can generally be used by the next instruction; if the result is not
available right away, the processor stalls until it is available. CP0 registers
and the TLB are not interlocked, however; there may be some delay before
a value written by one instruction is available to following instructions.
There is a required-data dependence between an instruction that changes a
register or TLB entry (a writer) and the next instruction that uses it (a user).
(A writer can write multiple data items, forming multiple writer/user
pairs.) The writer/user instruction pair places a hazard on the data if there
must be a delay between the time the writer instruction writes the data,
and the user instruction can use the data.
In addition to instructions, events can be writers and users of CP0
information. For instance, an exception writes information to CP0
registers and events that occur for every instruction, like an instruction
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