Appendix F
F-2 MIPS R4000 Microprocessor User's Manual
fetch, use CP0 information. Therefore, when manipulating CP0 contents,
the systems programmer must identify hazards and write code that avoids
these hazards.
Table F-1 describes how to identify and avoid hazards, listing instructions
and events that use CP0 registers and the TLB. This table also tells when
written information is available (column 3) and when this latest
information can actually be used (column 2). Exception event writer timing
refers to the instruction identified with the exception; user event timing
information is the pipestage of each instruction during which the user
event uses the data. In the case of a hazard, the number of instructions
required between a writer and user is:
available_stage - (use_stage + 1)
To identify a hazard, look for an instruction/event writer/user pair that
has a required-data dependence and use the timing information in the
table to calculate the delay required between the writer and user. If no
delay is required, there is no hazard. If there is a hazard, place enough
instructions between the writer and user so that the written information is
available or effective when the user needs it.
NOTE: Any instructions inserted between a writer/reader pair with
a hazard must not depend on or modify the data creating the hazard
(for example NOP instructions may be used).
The following steps are used to determine a hazard delay:
1. Find the pipeline stage of the writer instruction in which the result
is available. For example, the MTC0 instruction writes a CP0
general register, and the new value is available at stage 7.
2. Find the pipeline stage in which the user instruction reads or uses
the data item that the writer changes. The TLBWR instruction, for
example, uses different registers through different stages; all source
register values must be stable by stage 5 and remain unchanged
through stage 8.
3. Calculate the number of instructions that must be inserted between
the hazardous pair, by using this formula: available_stage -
(use_stage + 1). For example, with an MTC0/TLBWR pair, MTC0
data is available at stage 7, and TLBWR data must be stable by
stage 5 so the computation is: 7 - (5 + 1) = 1. This means 1
instruction must be inserted between the MTC0 and TLBWR. If the
result of the computation is less than or equal to zero, there is no
hazard and no instructions are required between the pair.
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