Chapter 3
60 MIPS R4000 Microprocessor User's Manual
Figure 3-13 Back-to-Back Uncached Stores in a Loop
The timing requirements of the System interface govern the latency
between uncached stores; back-to-back stores can be sent across the
interface at a maximum rate of one store for every four external cycles. If
the R4400 processor is programmed to run in divide-by-2 mode (for more
information about divided clock, see the description of SClock in Chapter
10), an uncached store can occur every eight pipeline cycles. If a larger
clock divisor is used, more pipeline cycles are required for each store.
CAUTION: The R4000 processor always had a strongly-ordered
execution; however, with the addition of the uncached store buffer in
the R4400 there is a potential for out-of-order execution (described in
the section of the same name in Chapter 11, and Uncached Loads or
Stores in Chapter 12).
Loop: SW R2, (R3) # uncached store
NOP
NOP
NOP
B Loop # branch to loop
NOP
killed # branch latency
killed # branch latency
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