Chapter 12
332 MIPS R4000 Microprocessor User's Manual
Figure 12-18 Processor Read Request Protocol, Change to Slave State Delayed
When the following three events occur—a read request is pending,
ExtRqst* is asserted, and Release* is asserted for one cycle—it may be
unclear if the assertion of Release* is in response to ExtRqst*, or
represents an uncompelled change to slave state. The only situation in
which the assertion of Release* cannot be considered an uncompelled
change to slave state is if the following three conditions exist
simultaneously:
• the System interface is operating in secondary-cache mode
• the read request was a read-with-write-forthcoming request
• the expected write request has not been issued by the
processor.
If these three conditions exist, the processor cannot accept the read
response; rather, it accepts the external request. The write request must be
accepted by the external agent before the read response can be issued.
In all other cases, the assertion of Release* indicates either an
uncompelled change to slave state, or a response to the assertion of
ExtRqst*, whereupon the processor accepts either a read response, or any
other external request. If any external request other than a read response
is issued, the processor performs another uncompelled change to slave
state, asserting Release*, after processing the external request.
SCycle
1 2 3 4 5 6 7 8 9 10 11 12
SClock
SysAD Bus
Addr
SysCmd Bus
Read
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
3
4
2
5
Master
Slave
1
6
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