Mips Technologies R4000 - Page 124

Chapter 4
94 MIPS R4000 Microprocessor User's Manual
Figure 4-18 TagLo and TagHi Register (P-cache) Formats
Figure 4-19 TagLo and TagHi Register (S-cache) Formats
Table 4-13 Cache Tag Register Fields
Field Description
PTagLo Specifies the physical address bits 35:12
PState Specifies the primary cache state
P Specifies the primary tag even parity bit
STagLo Specifies the physical address bits 35:17
SState Specifies the secondary cache state
VIndex
Specifies the virtual index of the associated Primary cache line,
vAddr(14:12)
ECC ECC for the STag, SState, and VIndex fields
0 Reserved. Must be written as zeroes, and returns zeroes when read.
Undefined The TagHi register should not be used.
31
0
32
TagLo
TagHi
31
1
0
24
P
87
PState
65 1
52
0PTagLo
Undefined
31 0
32
Undefined
TagLo
TagHi
31
7
70
19
ECC
STagLo
13 12
SState
10 9
VIndex
6
33