MIPS R4000 Microprocessor User's Manual 29
Introduction
Table 1-19 System Control Coprocessor (CP0) Register Definitions
Number Register Description
0 Index Programmable pointer into TLB array
1 Random Pseudorandom pointer into TLB array (read only)
2 EntryLo0 Low half of TLB entry for even virtual address (VPN)
3 EntryLo1 Low half of TLB entry for odd virtual address (VPN)
4 Context
Pointer to kernel virtual page table entry (PTE) in 32-bit
addressing mode
5 PageMask TLB Page Mask
6 Wired Number of wired TLB entries
7 — Reserved
8 BadVAddr Bad virtual address
9 Count Timer Count
10 EntryHi High half of TLB entry
11 Compare Timer Compare
12 SR Status register
13 Cause Cause of last exception
14 EPC Exception Program Counter
15 PRId Processor Revision Identifier
16 Config Configuration register
17 LLAddr Load Linked Address
18 WatchLo Memory reference trap address low bits
19 WatchHi Memory reference trap address high bits
20 XContext Pointer to kernel virtual PTE table in 64-bit addressing mode
21–25 — Reserved
26 ECC
Secondary-cache error checking and correcting (ECC) and
Primary parity
27 CacheErr Cache Error and Status register
28 TagLo Cache Tag register
29 TagHi Cache Tag register
30 ErrorEPC Error Exception Program Counter
31 — Reserved
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