Chapter 5
126 MIPS R4000 Microprocessor User's Manual
In both the Reset* and NMI cases the processor jumps to the Reset
exception vector located in unmapped and uncached address space, so
that the cache and TLB contents need not be initialized to service this
exception. Typically, the Reset exception vector is located in PROM, and
system memory does not need to be initialized to handle the exception.
As previously noted, state machines interrupted by Reset* may cause
some register contents to be inconsistent with the other processor state.
Otherwise, on an exception caused by Reset* or NMI the contents of all
registers are preserved, except for:
• EW bit in the CacheErr register, which is reset to 0 (R4400 only)
• ErrorEPC register, which contains the restart PC
• ERL bit of the Status register, which is set to 1
• SR bit of the Status register, which is set to 1
• BEV bit of the Status register, which is set to 1
• TS bit of the Status register, which is set to 0
• PC is set to the reset vector 0xFFFF FFFF BFC0 0000
Soft reset exception processing is shown in Figure 5-16.
Servicing
The exception initiated by Reset* is intended to quickly reinitialize a
previously operating processor after a fatal error such as a Master/
Checker mismatch. The NMI can be used for purposes other than resetting
the processor while preserving cache and memory contents. For example,
the system might use an NMI to cause an immediate, controlled shutdown
when it detects an impending power failure.
The exceptions due to Reset* and NMI appear identical to software; both
exceptions jump to the Reset exception vector and have the Status register
SR bit set. Unless external hardware provides a way to distinguish
between the two, they are serviced by saving the current user-visible
processor state for diagnostic purposes and reinitializing as for the Reset
exception. It is not normally possible to continue program execution after
returning from this exception, since a Reset* signal can be accepted
anytime and an NMI can occur in the midst of another error exception.
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