MIPS R4000 Microprocessor User's Manual xix
Table of Contents
6
Floating-Point Unit
Overview ...................................................................................................................152
FPU Features............................................................................................................. 153
FPU Programming Model.......................................................................................154
Floating-Point General Registers (FGRs).......................................................... 154
Floating-Point Registers...................................................................................... 156
Floating-Point Control Registers ....................................................................... 157
Implementation and Revision Register, (FCR0).............................................. 158
Control/Status Register (FCR31).......................................................................159
Accessing the Control/Status Register......................................................... 160
IEEE Standard 754 ........................................................................................... 161
Control/Status Register FS Bit....................................................................... 161
Control/Status Register Condition Bit......................................................... 161
Control/Status Register Cause, Flag, and Enable Fields...........................161
Control/Status Register Rounding Mode Control Bits.............................. 163
Floating-Point Formats............................................................................................164
Binary Fixed-Point Format...................................................................................... 166
Floating-Point Instruction Set Overview..............................................................167
Floating-Point Load, Store, and Move Instructions........................................169
Transfers Between FPU and Memory...........................................................169
Transfers Between FPU and CPU..................................................................169
Load Delay and Hardware Interlocks..........................................................169
Data Alignment................................................................................................ 170
Endianness........................................................................................................170
Floating-Point Conversion Instructions............................................................170
Floating-Point Computational Instructions.....................................................170
Branch on FPU Condition Instructions............................................................. 170
Floating-Point Compare Operations................................................................. 171
FPU Instruction Pipeline Overview....................................................................... 172
Instruction Execution ..........................................................................................172
Instruction Execution Cycle Time .....................................................................173
Scheduling FPU Instructions..............................................................................175
FPU Pipeline Overlapping..................................................................................175
Instruction Scheduling Constraints ..............................................................176
Instruction Latency, Repeat Rate, and Pipeline Stage Sequences.............181
Resource Scheduling Rules ............................................................................ 182
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