Mips Technologies R4000 - Page 21

MIPS R4000 Microprocessor User's Manual xxi
Table of Contents
9
Initialization Interface
Functional Overview ...............................................................................................214
Reset Signal Description.......................................................................................... 215
Power-on Reset..................................................................................................... 216
Cold Reset .............................................................................................................217
Warm Reset........................................................................................................... 217
Initialization Sequence............................................................................................. 218
Boot-Mode Settings.................................................................................................. 222
10
Clock Interface
Signal Terminology.................................................................................................. 228
Basic System Clocks.................................................................................................229
MasterClock..........................................................................................................229
MasterOut .............................................................................................................229
SyncIn/SyncOut...................................................................................................229
PClock.................................................................................................................... 229
SClock....................................................................................................................230
TClock....................................................................................................................230
RClock....................................................................................................................230
PClock-to-SClock Division .................................................................................230
System Timing Parameters .....................................................................................233
Alignment to SClock............................................................................................233
Alignment to MasterClock .................................................................................233
Phase-Locked Loop (PLL)................................................................................... 233
Connecting Clocks to a Phase-Locked System..................................................... 234
Connecting Clocks to a System without Phase Locking.....................................235
Connecting to a Gate-Array Device ..................................................................235
Connecting to a CMOS Logic System...............................................................238
Processor Status Outputs ........................................................................................ 241