Mips Technologies R4000 - Page 236

Chapter 8
206 MIPS R4000 Microprocessor User's Manual
Table 8-3 (cont.) Secondary Cache Interface Signals
Name Definition Direction Description
SCDChk(15:0)
Secondary cache
data ECC bus
Input/Output
A 16-bit bus that carries two 8-bit
ECC fields that cover the 128 bits
of SCData from/to secondary
cache. SCDChk(15:8)
corresponds to SCData(127:64)
and SCDChk(7:0) corresponds to
SCData(63:0).
SCDCS*
Secondary cache
data chip select
Output
Chip select enable signal for the
secondary cache data RAM.
SCOE*
Secondary cache
output enable
Output
Output enable for the secondary
cache data and tag RAM.
SCTag(24:0)
Secondary cache
tag bus
Input/Output
A 25-bit bus used to read or write
cache tags from and to the
secondary cache.
SCTChk(6:0)
Secondary cache
tag ECC bus
Input/Output
A 7-bit bus that carries an ECC
field covering the SCTag from and
to the secondary cache.
SCTCS*
Secondary cache
tag chip select
Output
Chip select enable signal for the
secondary cache tag RAM.
SCWrW*
Secondary cache
write enable
Output
Write enable for the secondary
cache data and tag RAM.
SCWrX*
Secondary cache
write enable
Output
Write enable for the secondary
cache data and tag RAM.
SCWrY*
Secondary cache
write enable
Output
Write enable for the secondary
cache data and tag RAM.
SCWrZ*
Secondary cache
write enable
Output
Write enable for the secondary
cache data and tag RAM.