MIPS R4000 Microprocessor User's Manual 253
Cache Organization, Operation, and Coherency
The R4000 processor secondary cache has the following characteristics:
• write-back
• direct-mapped
• indexed with a physical address
• checked with a physical tag
• organized with either a 4-word (16-byte), 8-word (32-byte),
16-word (64-byte), or 32-word (128-byte) cache line.
The secondary cache state (CS) bits indicate whether:
• the cache line data and tag are valid
• the data is potentially present in the caches of other processors
(shared versus exclusive)
• the processor is responsible for updating main memory (clean
versus dirty).
The PIdx field provides the processor with an index to the virtual address
of primary cache lines that may contain data from the secondary cache
line.
The PIdx field also detects a cache alias. Cache aliasing occurs when the
physical address tag matches during a data reference to the secondary
cache, but the PIdx field does not match in the virtual address. This
indicates that the cache reference was made from a different virtual
address than the one that created the secondary-cache line, and the
processor signals a Virtual Coherency exception.
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