Mips Technologies R4000 - Page 321

MIPS R4000 Microprocessor User's Manual 291
Cache Organization, Operation, and Coherency
Figure 11-19 shows synchronization using a counter.
Figure 11-19 Counter Using LL and SC
Loop1: LL r2,(r1)
BLEZ r2,Loop1
SUB r3,r2,1
NOP
SC r3,(r1)
BEQ r3,0,Loop1
NOP
.
.
.
.
Load counter
Successful?
Try decrementing
No
Yes
Execute critical section
Counter > 0?
Yes
No
counter
Load counter
Try incrementing
counter
Successful?
No
Yes
Continue processing
Loop2: LL r2,(r1)
ADDr3,r2,1
SC r3,(r1)
BEQ r3,0,Loop2
NOP
(r3=0?)