MIPS R4000 Microprocessor User's Manual 305
System Interface
Processor requests are managed by the processor in two distinct modes:
secondary-cache mode and no-secondary-cache mode (see Chapter 11 for a
description of these two modes), which are programmable through the
boot-time mode control interface described in Chapter 9.
The permissible modes of operation are dependent on the following
processor package configurations; if not programmed correctly, the
behavior of the processor is undefined.
• An R4000PC must be programmed to run in no-secondary-
cache mode.
• An R4000SC or R4000MC can be programmed to run in either
secondary-cache or no-secondary-cache mode.
In no-secondary-cache mode, the processor issues requests in a strict
sequential fashion; that is, the processor is only allowed to have one
request pending at any time. For example, the processor issues a read
request and waits for a read response before issuing any subsequent
requests. The processor submits a write request only if there are no read
requests pending.
The processor has the input signals RdRdy* and WrRdy* to allow an
external agent to manage the flow of processor requests. RdRdy* controls
the flow of processor read, invalidate, and update requests, while WrRdy*
controls the flow of processor write requests. Processor null write requests
must always be accepted and cannot be delayed by either RdRdy* or
WrRdy*. The processor request cycle sequence is shown in Figure 12-8.
Figure 12-8 Processor Request
R4000
External Agent
1. Processor issues read, write,
invalidate, or update request
2. External system controls
acceptance of requests by
asserting RdRdy* or WrRdy*
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