MIPS R4000 Microprocessor User's Manual A-19
CPU Instruction Set Details
Format:
BCzFL offset
Description:
A branch target address is computed from the sum of the address of the
instruction in the delay slot and the 16-bit offset, shifted left two bits and
sign-extended. If the contents of coprocessor z’s condition line, as
sampled during the previous instruction, is false, the target address is
branched to with a delay of one instruction.
If the conditional branch is not taken, the instruction in the branch delay
slot is nullified.
Because the condition line is sampled during the previous instruction,
there must be at least one instruction between this instruction and a
coprocessor instruction that changes the condition line.
*See the table “Opcode Bit Encoding” on next page, or “CPU Instruction
Opcode Bit Encoding” at the end of Appendix A.
BCzFL
5
16 15
BC
31 2526
COPz
6
0
16
offsetBCFL
21 20
5
0 1 0 0 x x* 0 1 0 0 0 0 0 0 1 0
BCzFL
Branch On Coprocessor z
False Likely
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