MIPS R4000 Microprocessor User's Manual A-25
CPU Instruction Set Details
Format:
BEQ rs, rt, offset
Description:
A branch target address is computed from the sum of the address of the
instruction in the delay slot and the 16-bit offset, shifted left two bits and
sign-extended. The contents of general register rs and the contents of
general register rt are compared. If the two registers are equal, then the
program branches to the target address, with a delay of one instruction.
Operation:
Exceptions:
None
BEQ
Branch On Equal
BEQ
31 2526 2021 1516 0
BEQ rs rt
offset
655 16
0 0 0 1 0 0
32 T: target ← (offset
15
)
14
|| offset || 0
2
condition ← (GPR[rs] = GPR[rt])
T+1: if condition then
PC ← PC + target
endif
64 T: target ← (offset
15
)
46
|| offset || 0
2
condition ← (GPR[rs] = GPR[rt])
T+1: if condition then
PC ← PC + target
endif
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