Appendix A
A-34 MIPS R4000 Microprocessor User's Manual
Format:
BLEZL rs, offset
Description:
A branch target address is computed from the sum of the address of the
instruction in the delay slot and the 16-bit offset, shifted left two bits and
sign-extended. The contents of general register rs is compared to zero. If
the contents of general register rs have the sign bit set, or are equal to zero,
then the program branches to the target address, with a delay of one
instruction.
If the conditional branch is not taken, the instruction in the branch delay
slot is nullified.
Operation:
Exceptions:
None
BLEZL
Branch on Less Than
31 2526 2021 1516 0
BLEZL rs 0
offset
655 16
Or Equal To Zero Likely
0 1 0 1 1 0 0 0 0 0 0
BLEZL
32 T: target ← (offset
15
)
14
|| offset || 0
2
condition ← (GPR[rs]
31
= 1) or (GPR[rs] = 0
32
)
T+1: if condition then
PC ← PC + target
endif
else
NullifyCurrentInstruction
64 T: target ← (offset
15
)
46
|| offset || 0
2
condition ← (GPR[rs]
63
= 1) or (GPR[rs] = 0
64
)
T+1: if condition then
PC ← PC + target
else
NullifyCurrentInstruction
endif
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