MIPS R4000 Microprocessor User's Manual A-37
CPU Instruction Set Details
Format:
BLTZALL rs, offset
Description:
A branch target address is computed from the sum of the address of the
instruction in the delay slot and the 16-bit offset, shifted left two bits and
sign-extended. Unconditionally, the address of the instruction after the
delay slot is placed in the link register, r31. If the contents of general
register rs have the sign bit set, then the program branches to the target
address, with a delay of one instruction.
General register rs may not be general register 31, because such an
instruction is not restartable. An attempt to execute this instruction with
register 31 specified as rs is not trapped, however. If the conditional
branch is not taken, the instruction in the branch delay slot is nullified.
Operation:
Exceptions:
None
BLTZALL
Than Zero And Link Likely
Branch On Less
31 2526 2021 1516 0
REGIMM rs BLTZALL
offset
655 16
0 0 0 0 0 1 1 0 0 1 0
BLTZALL
32 T: target ← (offset
15
)
14
|| offset || 0
2
condition ← (GPR[rs]
31
= 1)
T+1: if condition then
PC ← PC + target
endif
GPR[31] ← PC + 8
NullifyCurrentInstruction
else
64 T: target ← (offset
15
)
46
|| offset || 0
2
condition ← (GPR[rs]
63
= 1)
T+1: if condition then
PC ← PC + target
endif
GPR[31] ← PC + 8
NullifyCurrentInstruction
else
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