MIPS R4000 Microprocessor User's Manual A-55
CPU Instruction Set Details
Format:
DDIV rs, rt
Description:
The contents of general register rs are divided by the contents of general
register rt, treating both operands as 2’s complement values. No overflow
exception occurs under any circumstances, and the result of this operation
is undefined when the divisor is zero.
This instruction is typically followed by additional instructions to check
for a zero divisor and for overflow.
When the operation completes, the quotient word of the double result is
loaded into special register LO, and the remainder word of the double
result is loaded into special register HI.
If either of the two preceding instructions is MFHI or MFLO, the results of
those instructions are undefined. Correct operation requires separating
reads of HI or LO from writes by two or more instructions.
This operation is only defined for the R4000 operating in 64-bit mode.
Execution of this instruction in 32-bit mode causes a reserved instruction
exception.
Operation:
Exceptions:
Reserved instruction exception (R4000 in 32-bit mode)
DDIV
Doubleword Divide
31 2526 2021 1516 0
rs rt
655
65
10 6
SPECIAL 0 DDIV
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0
DDIV
← undefined
← undefined
← undefined
HI ← GPR[rs] mod GPR[rt]
T–2: LO ← undefined
T: LO ← GPR[rs] div GPR[rt]
HI
T–1: LO
HI
64
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