Mips Technologies R4000 - Page 569

MIPS R4000 Microprocessor User's Manual A-101
CPU Instruction Set Details
Operation:
Exceptions:
TLB refill exception TLB invalid exception
Bus error exception Address error exception
Coprocessor unusable exception
Opcode Bit Encoding:
(continued)
LWCz
Load Word To Coprocessor
LWCz
32 T: vAddr ← ((offset
15
)
16
|| offset
15...0
) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
PSIZE-1...3
|| (pAddr
2...0
xor (ReverseEndian || 0
2
))
mem ← LoadMemory (uncached, WORD, pAddr, vAddr, DATA)
byte ← vAddr
2...0
xor (BigEndianCPU || 0
2
)
COPzLW (byte, rt, mem)
64 T: vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR[base}
(pAddr, uncached)← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
PSIZE-1...3
|| (pAddr
2...0
xor (ReverseEndian || 0
2
))
mem ← LoadMemory (uncached, WORD, pAddr, vAddr, DATA)
byte ← vAddr
2...0
xor (BigEndianCPU || 0
2
)
COPzLW (byte, rt, mem)
LWCz
100011
31 30 29 28 27 26
Bit #
0
LWC1
100101
31 30 29 28 27 26
Bit #
0
LWC2
Coprocessor Unit Number
Opcode