Mips Technologies R4000 - Page 628

Appendix A
A-160 MIPS R4000 Microprocessor User's Manual
Given a doubleword in a register and a doubleword in memory, the
operation of SWR is as follows:
LEM Little-endian memory (BigEndianMem = 0)
BEM BigEndianMem = 1
Type AccessType (see Table 2-1) sent to memory
Offset pAddr
2...0
sent to memory
Exceptions:
TLB refill exception
TLB invalid exception
TLB modification exception
Bus error exception
Address error exception
SWR
Store Word Right
SWR
(Continued)
SWR
ACDB
Register
IKLJ
Memory
EGHF
MOPN
0IJKLEFGH304HJKLMNOP070
1IJKLFGHP214GHKLMNOP160
2IJKLGHOP124FGHLMNOP250
3IJKLHNOP034EFGHMNOP340
4EFGHMNOP340IJKLHNOP034
5FGHLMNOP250IJKLGHOP124
6GHKLMNOP160IJKLFGHP214
7HJKLMNOP070IJKLEFGH304
offset
BigEndianCPU = 1
BigEndianCPU = 0
offset
LEM BEM
LEM BEM
vAddr
2..0
type
destination
destination
type