MIPS R4000 Microprocessor User's Manual 47
The CPU Pipeline
WB - Write Back
For register-to-register instructions, the instruction result is written back
to the register file during the WB stage. Branch instructions perform no
operation during this stage.
Figure 3-2 shows the activities occurring during each ALU pipeline stage,
for load, store, and branch instructions.
Figure 3-2 CPU Pipeline Activities
IC1 Instruction cache access stage 1
IC2 Instruction cache access stage 2
ITLB1 Instruction address translation stage 1
ITLB2 Instruction address translation stage 2
ITC Instruction tag check
IDEC Instruction decode
RF Register operand fetch
ALU Operation
DVA Data virtual address calculation
DC1 Data cache access stage 1
DC2 Data cache access stage 2
LSA Data load or store align
JTLB1 Data/Instruction address translation stage 1
JTLB2 Data/Instruction address translation stage 2
DTC Data tag check
IVA Instruction virtual address calculation
WB Write back to register file
Clock
Phase
Stage
IFetch
ALU
Load/Store
Branch
12
IF IS RF EX DF DS TC WB
IC1 IC2
ITLB1 ITLB2 ITC
IDEC
RF
DVA DC1 DC2
LSA
JTLB1 JTLB2 DTC WB
IVA
121212121212 12
and
Decode
WB
ALU
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