NXP Semiconductors KL25 Series - Page 146

Table 7-2. Module operation in low power modes (continued)
Modules VLPR VLPW Stop VLPS LLS VLLSx
SPI1 master mode 2
Mbps,
slave mode 1
Mbps
static, slave
mode receive in
CPO
master mode 2
Mbps,
slave mode 1
Mbps
static, slave
mode receive
static, slave
mode receive
static OFF
I
2
C0 50 kbps
static, address
match wakeup
in CPO
50 kbps static, address
match wakeup
FF in PSTOP2
static, address
match wakeup
static OFF
I
2
C1 50 kbps
static, address
match wakeup
in CPO
50 kbps static, address
match wakeup
static, address
match wakeup
static OFF
Timers
TPM FF
Async operation
in CPO
FF Async operation
FF in PSTOP2
Async operation static OFF
PIT FF
static in CPO
FF static static static OFF
LPTMR FF FF Async operation
FF in PSTOP2
Async operation Async operation Async
operation
4
RTC FF
Async operation
in CPO
FF Async operation
FF in PSTOP2
Async operation Async operation Async
operation
5
Analog
16-bit ADC FF
ADC internal
clock only in
CPO
FF ADC internal
clock only
FF in PSTOP2
ADC internal
clock only
static OFF
CMP
6
FF
HS or LS
compare in CPO
FF HS or LS
compare
FF in PSTOP2
HS or LS
compare
LS compare LS compare in
VLLS1/3, OFF in
VLLS0
6-bit DAC FF
static in CPO
FF static
FF in PSTOP2
static static static, OFF in
VLLS0
12-bit DAC FF
static in CPO
FF static
FF in PSTOP2
static static static
Human-machine interfaces
GPIO FF
IOPORT write
only in CPO
FF static output,
wakeup input
FF in PSTOP2
static output,
wakeup input
static, pins
latched
OFF, pins
latched
Table continues on the next page...
Module Operation in Low Power Modes
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
146 Freescale Semiconductor, Inc.