NXP Semiconductors KL25 Series - Page 27

Section number Title Page
Chapter 37
Serial Peripheral Interface (SPI)
37.1 Introduction...................................................................................................................................................................655
37.1.1 Features........................................................................................................................................................655
37.1.2 Modes of Operation.....................................................................................................................................656
37.1.3 Block Diagrams............................................................................................................................................657
37.2 External Signal Description..........................................................................................................................................659
37.2.1 SPSCK — SPI Serial Clock.........................................................................................................................659
37.2.2 MOSI — Master Data Out, Slave Data In...................................................................................................660
37.2.3 MISO — Master Data In, Slave Data Out...................................................................................................660
37.2.4 SS — Slave Select........................................................................................................................................660
37.3 Memory Map and Register Descriptions......................................................................................................................661
37.3.1 SPI control register 1 (SPIx_C1)..................................................................................................................661
37.3.2 SPI control register 2 (SPIx_C2)..................................................................................................................663
37.3.3 SPI baud rate register (SPIx_BR).................................................................................................................664
37.3.4 SPI status register (SPIx_S).........................................................................................................................665
37.3.5 SPI data register (SPIx_D)...........................................................................................................................667
37.3.6 SPI match register (SPIx_M).......................................................................................................................668
37.4 Functional Description..................................................................................................................................................668
37.4.1 General.........................................................................................................................................................668
37.4.2 Master Mode................................................................................................................................................669
37.4.3 Slave Mode..................................................................................................................................................670
37.4.4 SPI Transmission by DMA..........................................................................................................................671
37.4.5 SPI Clock Formats.......................................................................................................................................673
37.4.6 SPI Baud Rate Generation...........................................................................................................................676
37.4.7 Special Features...........................................................................................................................................677
37.4.8 Error Conditions...........................................................................................................................................678
37.4.9 Low Power Mode Options...........................................................................................................................679
37.4.10 Reset.............................................................................................................................................................681
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 27