NXP Semiconductors KL25 Series - Page 307

19.31.2 MTB Master Register (MTB_MASTER)
The MTB_MASTER register contains the main program trace enable plus other trace
controls. This register can be modified by the explicit programming model writes.
MTB_MASTER[EN] and MTB_MASTER[HALTREQ] fields are also automatically
updated by the MTB hardware.
Before the MTB_MASTER[EN] or MTB_MASTER[TSTARTEN] bits are set to 1,
software must initialize the MTB_POSITION and MTB_FLOW registers.
If the MTB_FLOW[WATERMARK] field is used to stop tracing or to halt the processor,
the MTB_MASTER[MASK] field must still be set to a value that prevents the
MTB_POSITION[POINTER] field from wrapping before it reaches the
MTB_FLOW[WATERMARK] value.
NOTE
The format of this mask field is different than the
MTBDWT_MASKn[MASK].
Address: F000_0000h base + 4h offset = F000_0004h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
EN
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
HALTREQ
RAMPRIV
SFRWPRIV
TSTOPEN
TSTARTEN
MASK
W
Reset
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
MTB_MASTER field descriptions
Field Description
31
EN
Main trace enable bit
When this bit is 1, trace data is written into the RAM memory location addressed by
MTB_POSITION[POINTER]. The MTB_POSITION[POINTER] value auto increments after the trace data
packet is written.
The EN bit can be automatically set to 0 using the MTB_FLOW[WATERMARK] field and the
MTB_FLOW[AUTOSTOP] bit.
The EN bit is automatically set to 1 if the TSTARTEN bit is 1 and the TSTART signal is HIGH.
The EN bit is automatically set to 0 if TSTOPEN bit is 1 and the TSTOP signal is HIGH.
Table continues on the next page...
Chapter 19 Micro Trace Buffer (MTB)
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 307