NXP Semiconductors KL25 Series - Page 4

Section number Title Page
3.2 Module to Module Interconnects..................................................................................................................................45
3.2.1 Module to Module Interconnects.................................................................................................................45
3.2.2 Analog reference options.............................................................................................................................48
3.3 Core Modules................................................................................................................................................................48
3.3.1 ARM Cortex-M0+ Core Configuration.......................................................................................................48
3.3.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................51
3.3.3 Asynchronous wake-up interrupt controller (AWIC) configuration............................................................55
3.4 System Modules............................................................................................................................................................56
3.4.1 SIM Configuration.......................................................................................................................................56
3.4.2 System Mode Controller (SMC) Configuration...........................................................................................57
3.4.3 PMC Configuration......................................................................................................................................57
3.4.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................58
3.4.5 MCM Configuration....................................................................................................................................60
3.4.6 Crossbar-Light Switch Configuration..........................................................................................................61
3.4.7 Peripheral Bridge Configuration..................................................................................................................62
3.4.8 DMA request multiplexer configuration......................................................................................................63
3.4.9 DMA Controller Configuration...................................................................................................................66
3.4.10 Computer Operating Properly (COP) Watchdog Configuration..................................................................67
3.5 Clock Modules..............................................................................................................................................................70
3.5.1 MCG Configuration.....................................................................................................................................70
3.5.2 OSC Configuration......................................................................................................................................71
3.6 Memories and Memory Interfaces................................................................................................................................72
3.6.1 Flash Memory Configuration.......................................................................................................................72
3.6.2 Flash Memory Controller Configuration.....................................................................................................74
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
4 Freescale Semiconductor, Inc.