NXP Semiconductors KL25 Series - Page 5

Section number Title Page
3.6.3 SRAM Configuration...................................................................................................................................75
3.7 Analog...........................................................................................................................................................................77
3.7.1 16-bit SAR ADC Configuration..................................................................................................................77
3.7.2 CMP Configuration......................................................................................................................................81
3.7.3 12-bit DAC Configuration...........................................................................................................................83
3.8 Timers...........................................................................................................................................................................84
3.8.1 Timer/PWM Module Configuration............................................................................................................84
3.8.2 PIT Configuration........................................................................................................................................87
3.8.3 Low-power timer configuration...................................................................................................................88
3.8.4 RTC configuration.......................................................................................................................................90
3.9 Communication interfaces............................................................................................................................................91
3.9.1 Universal Serial Bus (USB) FS Subsystem.................................................................................................91
3.9.2 SPI configuration.........................................................................................................................................96
3.9.3 I2C Configuration........................................................................................................................................97
3.9.4 UART Configuration...................................................................................................................................98
3.10 Human-machine interfaces (HMI)................................................................................................................................99
3.10.1 GPIO Configuration.....................................................................................................................................99
3.10.2 TSI Configuration........................................................................................................................................101
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................105
4.2 System memory map.....................................................................................................................................................105
4.3 Flash Memory Map.......................................................................................................................................................106
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................106
4.4 SRAM memory map.....................................................................................................................................................107
4.5 Bit Manipulation Engine...............................................................................................................................................107
4.6 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................108
4.6.1 Read-after-write sequence and required serialization of memory operations..............................................108
4.6.2 Peripheral Bridge (AIPS-Lite) Memory Map..............................................................................................109
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 5