NXP Semiconductors KL25 Series - Page 6

Section number Title Page
4.6.3 Modules Restricted Access in User Mode...................................................................................................112
4.7 Private Peripheral Bus (PPB) memory map..................................................................................................................112
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................115
5.2 Programming model......................................................................................................................................................115
5.3 High-Level device clocking diagram............................................................................................................................115
5.4 Clock definitions...........................................................................................................................................................116
5.4.1 Device clock summary.................................................................................................................................117
5.5 Internal clocking requirements.....................................................................................................................................119
5.5.1 Clock divider values after reset....................................................................................................................119
5.5.2 VLPR mode clocking...................................................................................................................................120
5.6 Clock Gating.................................................................................................................................................................121
5.7 Module clocks...............................................................................................................................................................121
5.7.1 PMC 1-kHz LPO clock................................................................................................................................122
5.7.2 COP clocking...............................................................................................................................................122
5.7.3 RTC clocking...............................................................................................................................................123
5.7.4 LPTMR clocking..........................................................................................................................................123
5.7.5 TPM clocking...............................................................................................................................................124
5.7.6 USB FS OTG Controller clocking...............................................................................................................124
5.7.7 UART clocking............................................................................................................................................125
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................127
6.2 Reset..............................................................................................................................................................................127
6.2.1 Power-on reset (POR)..................................................................................................................................128
6.2.2 System reset sources....................................................................................................................................128
6.2.3 MCU Resets.................................................................................................................................................131
6.2.4 Reset Pin .....................................................................................................................................................133
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
6 Freescale Semiconductor, Inc.