NXP Semiconductors KL25 Series

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Table 3-20. DMA request sources - MUX 0 (continued)

Source

number

Source module Source description Async DMA

capable

8 Reserved —

9 Reserved —

10 Reserved —

11 Reserved —

12 Reserved —

13 Reserved —

14 Reserved —

15 Reserved —

16 SPI0 Receive

17 SPI0 Transmit

18 SPI1 Receive

19 SPI1 Transmit

20 Reserved —

21 Reserved —

22 I

C0 —

23 I

C1 —

24 TPM0 Channel 0 Yes

25 TPM0 Channel 1 Yes

26 TPM0 Channel 2 Yes

27 TPM0 Channel 3 Yes

28 TPM0 Channel 4 Yes

29 TPM0 Channel 5 Yes

30 Reserved —

31 Reserved —

32 TPM1 Channel 0 Yes

33 TPM1 Channel 1 Yes

34 TPM2 Channel 0 Yes

35 TPM2 Channel 1 Yes

36 Reserved —

37 Reserved —

38 Reserved —

39 Reserved —

40 ADC0 — Yes

41 Reserved —

42 CMP0 — Yes

43 Reserved —

44 Reserved —

45 DAC0 —

46 Reserved —

Table continues on the next page...

Chapter 3 Chip Configuration

KL25 Sub-Family Reference Manual, Rev. 3, September 2012

Freescale Semiconductor, Inc. 65

Main Page

Default Chapter3
- Table of Contents3
Chapter 1 About this Document33
- Overview33
  - Purpose33
  - Audience33
- Conventions33
Chapter 2 Introduction35
- Overview35
- Kinetis L Series35
- KL25 Sub-Family Introduction38
- Module Functional Categories39
- Orderable Part Numbers44
Chapter 3 Chip Configuration45
- Introduction45
- Module to Module Interconnects45
  - KL25 Sub-Family Reference Manual, Rev. 3, September46
  - Analog Reference Options48
- Core Modules48
- System Modules56
- Clock Modules70
  - MCG Configuration70
  - OSC Configuration71
- Memories and Memory Interfaces72
- Analog77
- Timers84
- Communication Interfaces91
- Human-Machine Interfaces (HMI)99
- Introduction105
- System Memory Map105
- Flash Memory Map106
Chapter 4 Alternate Non-Volatile IRC User Trim Description107
- SRAM Memory Map107
- Bit Manipulation Engine107
- Peripheral Bridge (AIPS-Lite) Memory Map108
- Private Peripheral Bus (PPB) Memory Map112
Chapter 5115
- Introduction115
- Programming Model115
- High-Level Device Clocking Diagram115
- Clock Definitions116
  - Device Clock Summary117
- Internal Clocking Requirements119
  - Clock Divider Values after Reset119
  - VLPR Mode Clocking120
- Clock Gating121
- Module Clocks121
Chapter 6 Reset and Boot127
- Introduction127
- Reset127
- Boot134
Chapter 7 Power Management137
- Introduction137
- Clocking Modes137
- Power Modes141
- Entering and Exiting Power Modes143
- Module Operation in Low Power Modes143
Chapter 8 Security149
- Introduction149
- Flash Security149
- Security Interactions with Other Modules149
  - Security Interactions with Debug150
Chapter 9 Debug151
- Introduction151
- Debug Port Pin Descriptions151
- SWD Status and Control Registers152
Chapter 10160
- Port Control and Interrupt Module Features160
- Clock Gating161
- KL25 Pinouts164
- Module Signal Description Tables168
  - Core Modules169
  - Modes of Operation176
- External Signal Description176
- KL25 Sub-Family Reference Manual, Rev. 3, September176
- Detailed Signal Description177
- Memory Map and Register Definition177
- Functional Description187
Chapter 12 System Integration Module (SIM)191
- Introduction191
  - Features191
- Memory Map and Register Definition191
- Functional Description216
Chapter 13 System Mode Controller (SMC)217
- Introduction217
- Modes of Operation217
- Memory Map and Register Descriptions219
- Functional Description224
Chapter 14 Power Management Controller (PMC)237
- Introduction237
- Features237
- Low-Voltage Detect (LVD) System237
- I/O Retention239
- Memory Map and Register Descriptions239
Chapter 15 Low-Leakage Wakeup Unit (LLWU)245
- Introduction245
- LLWU Signal Descriptions248
- Memory Map/Register Definition248
- Functional Description262
Chapter 16 Reset Control Module (RCM)265
- Introduction265
- Reset Memory Map and Register Descriptions265
Chapter 17 Bit Manipulation Engine (BME)271
- Introduction271
- External Signal Description273
- Memory Map and Register Definition274
- Functional Description274
- Application Information288
Chapter 18 Miscellaneous Control Module (MCM)291
- Introduction291
  - Features291
- Memory Map/Register Descriptions291
Chapter 19 Micro Trace Buffer (MTB)299
- Introduction299
- External Signal Description303
- Memory Map and Register Definition304
Chapter 20 Crossbar Switch Lite (AXBS-Lite)331
- Introduction331
  - Features331
- Memory Map / Register Definition331
- Functional Description332
  - General Operation332
  - Arbitration333
- Initialization/Application Information334
Chapter 21 Peripheral Bridge (AIPS-Lite)335
- Introduction335
  - Features335
  - General Operation336
- Functional Description336
  - Access Support336
Chapter 22 Direct Memory Access Multiplexer (DMAMUX)337
- Introduction337
- External Signal Description339
- Memory Map/Register Definition339
  - Channel Configuration Register (Dmamuxx_Chcfgn)339
- Functional Description340
- Initialization/Application Information344
  - Reset344
  - Enabling and Configuring Sources344
Chapter 23 DMA Controller Module349
- Introduction349
  - Overview349
  - Features350
- DMA Transfer Overview351
- Memory Map and Registers352
- Functional Description361
Chapter 24372
- MCG Control 1 Register (MCG_C1)372
- MCG Control 2 Register (MCG_C2)373
- MCG Control 3 Register (MCG_C3)374
- Freescale Semiconductor, Inc375
- MCG Control 5 Register (MCG_C5)376
- MCG Control 6 Register (MCG_C6)377
- MCG Status Register (MCG_S)378
- Freescale Semiconductor, Inc379
- MCG Status and Control Register (MCG_SC)380
- MCG Auto Trim Compare Value High Register (MCG_ATCVH)381
- MCG Control 7 Register (MCG_C7)382
- MCG Control 9 Register (MCG_C9)383
  - Functional Description384
  - Freescale Semiconductor, Inc385
  - Freescale Semiconductor, Inc386
  - Freescale Semiconductor, Inc387
- MCG Internal Reference Clocks388
- Low Power Bit Usage388
- External Reference Clock389
- MCG Fixed Frequency Clock389
- KL25 Sub-Family Reference Manual, Rev. 3, September389
- MCG PLL Clock390
- MCG Auto TRIM (ATM)390
- Initialization / Application Information391
  - MCG Module Initialization Sequence391
  - Freescale Semiconductor, Inc392
  - Using a 32.768 Khz Reference393
  - Freescale Semiconductor, Inc393
  - MCG Mode Switching394
Chapter 25 Oscillator (OSC)405
- Introduction405
- Features and Modes405
- Block Diagram406
- OSC Signal Descriptions406
- External Crystal / Resonator Connections407
- External Clock Connections408
- Memory Map/Register Definitions409
  - OSC Memory Map/Register Definition409
- Functional Description410
- Reset414
- Low Power Modes Operation414
- Interrupts414
Chapter 42420
- Features420
Chapter 26 Glossary421
- External Signal Description422
- Flash Configuration Field Description423
- Register Descriptions424
- Flash Protection433
- Flash Operation in Low-Power Modes434
- Flash Reads and Ignored Writes435
- Margin Read Commands440
- Flash Command Description441
- Security454
Chapter 28 ADC Signal Descriptions459
- Voltage Reference Select460
- Analog Channel Inputs (Adx)461
- ADC Status and Control Registers 1 (Adcx_Sc1N)462
  - Freescale Semiconductor, Inc463
  - Freescale Semiconductor, Inc464
- ADC Configuration Register 1 (Adcx_Cfg1)465
- Freescale Semiconductor, Inc466
- ADC Configuration Register 2 (Adcx_Cfg2)467
- ADC Data Result Register (Adcx_Rn)468
- Compare Value Registers (Adcx_Cvn)469
- Status and Control Register 2 (Adcx_Sc2)470
- Freescale Semiconductor, Inc471
- Status and Control Register 3 (Adcx_Sc3)472
- Freescale Semiconductor, Inc473
- ADC Offset Correction Register (Adcx_Ofs)474
- ADC Minus-Side Gain Register (Adcx_Mg)475
- ADC Plus-Side General Calibration Value Register (Adcx_Clps)476
- KL25 Sub-Family Reference Manual, Rev. 3, September477
- ADC Plus-Side General Calibration Value Register (Adcx_Clp1)478
- ADC Minus-Side General Calibration Value Register (Adcx_Clmd)479
- ADC Minus-Side General Calibration Value Register (Adcx_Clm4)480
- ADC Minus-Side General Calibration Value Register (Adcx_Clm2)481
- ADC Minus-Side General Calibration Value Register (Adcx_Clm0)482
- Clock Select and Divide Control483
- Voltage Reference Selection484
- Conversion Control485
  - Freescale Semiconductor, Inc486
  - Freescale Semiconductor, Inc487
  - Freescale Semiconductor, Inc488
  - Freescale Semiconductor, Inc489
  - Freescale Semiconductor, Inc490
  - Freescale Semiconductor, Inc491
  - Freescale Semiconductor, Inc492
- Automatic Compare Function493
- Calibration Function494
- Freescale Semiconductor, Inc495
- User-Defined Offset Function496
- Temperature Sensor497
- MCU Normal Stop Mode Operation498
- MCU Low-Power Stop Mode Operation499
  - KL25 Sub-Family Reference Manual, Rev. 3, September500
  - Application Information501
  - Freescale Semiconductor, Inc502
- Sources of Error503
  - Freescale Semiconductor, Inc504
  - Freescale Semiconductor, Inc505
  - Freescale Semiconductor, Inc506
  - Freescale Semiconductor, Inc507
  - Freescale Semiconductor, Inc508
  - Introduction509
Chapter 29510
- Bit DAC Key Features510
- ANMUX Key Features511
- CMP Block Diagram512
- CMP Interrupts533
- CMP Asyncrhonous DMA Support534
- KL25 Sub-Family Reference Manual, Rev. 3, September535
- DAC Interrupts536
Chapter 30540
- DAC Data High Register (Dacx_Datnh)540
- DAC Control Register (Dacx_C0)541
- DAC Control Register 1 (Dacx_C1)542
- Functional Description543
- DMA Operation544
  - Freescale Semiconductor, Inc545
  - Freescale Semiconductor, Inc546
  - Introduction547
  - Modes of Operation548
  - KL25 Sub-Family Reference Manual, Rev. 3, September549
  - TPM_EXTCLK — TPM External Clock550
  - Freescale Semiconductor, Inc551
- Status and Control (Tpmx_Sc)552
- Counter (Tpmx_Cnt)553
- Modulo (Tpmx_Mod)554
- Channel (N) Status and Control (Tpmx_Cnsc)555
- Freescale Semiconductor, Inc556
- Channel (N) Value (Tpmx_Cnv)557
- Freescale Semiconductor, Inc558
- Configuration (Tpmx_Conf)559
  - Freescale Semiconductor, Inc560
  - Functional Description561
- Prescaler562
- Freescale Semiconductor, Inc563
- Input Capture Mode564
- Output Compare Mode565
- Freescale Semiconductor, Inc566
- Edge-Aligned PWM (EPWM) Mode567
- Center-Aligned PWM (CPWM) Mode568
- Freescale Semiconductor, Inc569
- Registers Updated from Write Buffers570
- Reset Overview571
  - Freescale Semiconductor, Inc572
  - Introduction573
  - Features574
  - KL25 Sub-Family Reference Manual, Rev. 3, September575
  - Freescale Semiconductor, Inc576
- PIT Upper Lifetime Timer Register (PIT_LTMR64H)577
- Timer Load Value Register (Pit_Ldvaln)578
- Timer Control Register (Pit_Tctrln)579
- Timer Flag Register (Pit_Tflgn)580
- Freescale Semiconductor, Inc581
- Interrupts582
- Example Configuration for Chained Timers583
- Example Configuration for the Lifetime Timer584
  - Freescale Semiconductor, Inc585
  - Freescale Semiconductor, Inc586
Chapter 41 Introduction587
Chapter 33 LPTMR Signal Descriptions588
- Low Power Timer Control Status Register (Lptmrx_Csr)589
- Low Power Timer Prescale Register (Lptmrx_Psr)590
- Freescale Semiconductor, Inc591
- Low Power Timer Compare Register (Lptmrx_Cmr)592
- KL25 Sub-Family Reference Manual, Rev. 3, September593
- Freescale Semiconductor, Inc594
- LPTMR Compare595
- LPTMR Hardware Trigger596
- Introduction597
Chapter 34598
- RTC Signal Descriptions598
- RTC Time Seconds Register (RTC_TSR)599
- RTC Time Alarm Register (RTC_TAR)600
- RTC Control Register (RTC_CR)601
- Freescale Semiconductor, Inc602
- RTC Status Register (RTC_SR)603
- RTC Lock Register (RTC_LR)604
- RTC Interrupt Enable Register (RTC_IER)605
- Functional Description606
Chapter 35612
- USB On-The-Go612
- USB-FS Features613
- Programmers Interface614
- OTG and Host Mode Operation644
  - Freescale Semiconductor, Inc645
  - Freescale Semiconductor, Inc646
- On-The-Go Operation647
  - OTG Dual Role a Device Operation648
  - OTG Dual Role B Device Operation649
Chapter 37657
- Block Diagrams657
- Freescale Semiconductor, Inc658
- External Signal Description659
Chapter 38690
- I2C Address Register 1 (I2Cx_A1)690
- I2C Frequency Divider Register (I2Cx_F)691
- I2C Control Register 1 (I2Cx_C1)692
- Freescale Semiconductor, Inc693
- I2C Status Register (I2Cx_S)694
- I2C Data I/O Register (I2Cx_D)695
- I2C Control Register 2 (I2Cx_C2)696
- I2C Programmable Input Glitch Filter Register (I2Cx_Flt)697
- I2C Range Address Register (I2Cx_Ra)698
- I2C Smbus Control and Status Register (I2Cx_Smb)699
- Freescale Semiconductor, Inc700
- I2C Address Register 2 (I2Cx_A2)701
- Bit Address707
- Freescale Semiconductor, Inc708
- Address Matching709
- Programmable Input Glitch Filter714
- Address Matching Wakeup715
- DMA Support716
Chapter 39725
- UART Baud Rate Register High (Uartx_Bdh)725
- UART Baud Rate Register Low (Uartx_Bdl)726
- UART Match Address Registers 1 (Uartx_Ma1)735
- UART Match Address Registers 2 (Uartx_Ma2)736
- UART Control Register 5 (Uartx_C5)737
  - Functional Description738
  - KL25 Sub-Family Reference Manual, Rev. 3, September739
- Receiver Functional Description740
  - Freescale Semiconductor, Inc741
  - Freescale Semiconductor, Inc742
- Additional UART Functions743
- Freescale Semiconductor, Inc744
- Interrupts and Status Flags745
- Register Definition750
Chapter 40751
- UART Baud Rate Register: High (Uartx_Bdh)751
- UART Control Register 1 (Uartx_C1)752
- UART Control Register 2 (Uartx_C2)753
- Freescale Semiconductor, Inc754
- UART Status Register 1 (Uartx_S1)755
- UART Status Register 2 (Uartx_S2)756
- Freescale Semiconductor, Inc757
- UART Control Register 3 (Uartx_C3)758
- Freescale Semiconductor, Inc759
- UART Data Register (Uartx_D)760
- Functional Description761
- Baud Rate Generation762
- Freescale Semiconductor, Inc763
- Receiver Functional Description764
  - Freescale Semiconductor, Inc765
  - Freescale Semiconductor, Inc766
  - Interrupts and Status Flags767
  - DMA Operation768
  - KL25 Sub-Family Reference Manual, Rev. 3, September769
  - Freescale Semiconductor, Inc770
  - Introduction771
  - Modes of Operation772
  - Memory Map and Register Definition773
  - Freescale Semiconductor, Inc774
- Port Data Output Register (Gpiox_Pdor)775
- Port Set Output Register (Gpiox_Psor)776
- Port Toggle Output Register (Gpiox_Ptor)777
- Port Data Direction Register (Gpiox_Pddr)778
- Freescale Semiconductor, Inc779
- Port Data Output Register (Fgpiox_Pdor)780
- Port Set Output Register (Fgpiox_Psor)781
- Port Toggle Output Register (Fgpiox_Ptor)782
- Port Data Direction Register (Fgpiox_Pddr)783
- Ioport784
  - Introduction785
  - KL25 Sub-Family Reference Manual, Rev. 3, September786
  - External Signal Description787
  - Freescale Semiconductor, Inc788
  - Freescale Semiconductor, Inc789
  - Freescale Semiconductor, Inc790
  - Freescale Semiconductor, Inc791
- TSI DATA Register (Tsix_Data)792
- TSI Threshold Register (Tsix_Tshd)793
- Capacitance Measurement794
  - Freescale Semiconductor, Inc795
  - Freescale Semiconductor, Inc796
- TSI Measurement Result797
- Scan Times798
- Current Source799
- Wake up MCU from Low Power Modes800
  - KL25 Sub-Family Reference Manual, Rev. 3, September801
  - Freescale Semiconductor, Inc802
  - Freescale Semiconductor, Inc803
  - Freescale Semiconductor, Inc804
  - Freescale Semiconductor, Inc805
  - Freescale Semiconductor, Inc807

NXP Semiconductors KL25 Series - Page 65

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