Broadcom BCM5722 - Table 19: Status Block Format for BCM5755 and BCM5755 M Devices; Table 20: Status Word Flags

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Status Block Page 54
The BCM5755 and BCM5755M devices support four Receive Return Rings. The Status Block format for these devices is
given below.
The Status word field contains bit flags that contain error information about the status of the controller. The defined flags are
listed in the table below.
Table 19: Status Block Format for BCM5755 and BCM5755M Devices
Offset 31 16 15 0
0x00 Status Word
0x04 Status Tag
0x08 Receive Producer Ring Consumer Index
a
a. The Receive Standard Consumer Index is also accessible at 0x3C54.
Receive Return Ring 2 Producer Index
0x0C Receive Return Ring 3 Producer Index Receive Return Ring 4 Producer Index
0x10 Send Ring BD Consumer Index
b
b. The Send BD Consumer Index is also accessible at 0x3CC0.
Receive Return Ring 1 Producer Index
c
c. The Receive Return Ring BD Producer Indices are also accessible at 0x3C80–0x3C8F.
Table 20: Status Word Flags
Bits Name Description
0 Updated This bit is always set to 1 each time the status block is updated in the host via DMA. It is
expected that host software clear this bit in the status block each time it examines the
status block. This provides the host driver with a way of knowing whether the status block
has been updated since the last time the driver looked at the status block.
1 Link State Changed Indicates that link status has changed. This method of determining link change status
provides a small performance increase over doing a PIO read of the Ethernet MAC Status
register (see “Ethernet MAC Status Register (Offset 0x404)” on page 246. See “PHY
Setup and Initialization” on page 157 for a description of the PHY setup required when
link state changes.
2 Error When this bit is asserted by the chip, the following conditions may have occurred. Bit 2
of the status word is the OR of:
• All bits in Flow Attention register (0x3c48) (see “Flow Attention Register (Offset
0x3C48)” on page 297.
• MAC_ATTN—Events from the MAC block (see “Ethernet MAC Status Register (Offset
0x404)” on page 246.
• DMA_EVENT—Events from the following blocks:
- MSI (see “MSI Status Register (Offset 0x6004)” on page 330.
- DMA_RD (see “Read DMA Status Register (Offset 0x4804)” on page 313.
- DMA_WR (see “Write DMA Status Register (Offset 0x4C04)” on page 315.
• RXCP_ATTN—Events from RX RISC (see “RX RISC State Register (Offset 0x5004)”
on page 318.