Broadcom BCM5722 - Table 194: Ethernet MAC Address High Register (Offset 0 X410); Table 195: Ethernet MAC Address Low Register (Offset 0 X414); Table 196: WOL Pattern Pointer Register (Offset 0 X430)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 249 Ethernet MAC Control Registers Document 5722-PG101-R
ETHERNET MAC ADDRESSES REGISTERS (OFFSET 0X410–0X42C)
The Ethernet MAC needs to be initialized with up to four 6-byte MAC addresses in order to perform hardware receive packet
filtering. When operating the receive MAC in promiscuous mode, no receive filtering is performed. MAC address one is used
as the source address for sending flow-control packets. The addresses are not synchronized, so they must not be set after
initialization unless the MAC block is reset.
WOL PATTERN POINTER REGISTER (OFFSET 0X430)
Note: To enable either MAC Mode or Shared Traffic/Link LED Mode, the LED Mode (bits 12:11) must be set to MAC LED
mode (0x0).
Table 194: Ethernet MAC Address High Register (Offset 0x410)
Address Offset MAC Address 0: 0x410
Address Offset MAC Address 1: 0x418
Address Offset MAC Address 2: 0x420
Address Offset MAC Address 3: 0x428
Bit Field Description Init Access
31:16 Reserved Always 0. 0h RO
15:0 MAC Address High Upper 2-bytes of this node’s MAC address. 0h R/W
Table 195: Ethernet MAC Address Low Register (Offset 0x414)
Address Offset MAC Address 0: 0x414
Address Offset MAC Address 1: 0x41C
Address Offset MAC Address 2: 0x424
Address Offset MAC Address 3: 0x42C
Bit Field Description Init Access
31:0 MAC Address Low Lower 4-bytes of this node’s MAC address. 0h R/W
Table 196: WOL Pattern Pointer Register (Offset 0x430)
Bit Field Description Init Access
31:9 Reserved –
8:0 ACPI Pointer Specifies the offset into the 6-KB BD memory for frame
comparison. (Bits 3:0 are ignored to align the memory
address to a natural 128-bit boundary.)
0x000 R/W
Table 193: LED Control Register (Offset 0x40C) (Cont.)
Bit Field Description Init Access