Broadcom BCM5722 - Table 460: Link Pcie 1.1 Control Register (0 X7 D54)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R PCIe Registers Page 404
LINK PCIE 1.1 CONTROL REGISTER (0X7D54)
Table 460: Link PCIe 1.1 Control Register (0x7D54)
Bit Field Description Init Reset Access
31:29 Rtbf_ct[2:0] Timing debug control pins for the retry buffer,
normally 0. These bits are only writable when
enable_retry_buf_tim_mod in the TLP register
(0x7c04 bit31) is set
0 Chip
(hard +
soft)
RW
28:27 Rtbf_sam[1:0] Sense amp debug control pins for the retry
buffer, normally 0. These bits are only writable
when enable_retry_buf_tim_mod in the TLP
register (0x7c04 bit31) is set
0 Chip
(hard +
soft)
RW
26:16 Reserved Reserved bits 0 RO
15:12 Pcie_tmux_sel (BCM5787,
BCM5787M, BCM5754, and
BCM5754M only)
To select PCIe diagnostic bus in snoop and
serdes test modes
0x7 Hard
Reset
RW
Reserved (other devices) 0x0 RO
9 Select Local Xtal (BCM5787,
BCM5787M, BCM5754, and
BCM5754M only)
• 1 = To select local 25 MHz xtal as PCIe PLL
source clock.
• 0 = To select ref clock per refsel bonding as
PCIe PLL source clock. By default, the refsel
bonding selects 100 MHz PCIe ref clock.
0Hard
Reset
RW
Reserved (other devices) 0 RO
7 L1 PLL Powerdown Disable
• 1 = Disable PLL power down in L1
• 0 = Enable PLL power down in L1
1Hard
Reset
RW
6 L2 D3PM clkreq Disable
• 1 = Disable clkreq in L2 D3Cold
• 0 = Enable clkreq in L2 D3Cold
When clkreq is disabled, the device will not de-
assert CLKREQ# when entering the
corresponding low power modes
0Hard
Reset
RW
5 L1 D3PM clkreq Disable If this bit is set, the device will drive clkreq# low
which means the system will not turn off the
reference clock
• 1 = Disable clkreq in L1 D3Hot
• 0 = Enable clkreq in L1 D3Hot
When clkreq is disabled, our device will not de-
assert CLKREQ# when entering the
corresponding low power modes
0Hard
Reset
RW
4 L1 ASPM clkreq Disable
• 1 = Disable clkreq in L1 ASPM
• 0 = Enable clkreq in L1 ASPM
When clkreq is disabled, our device will not de-
assert CLKREQ# when entering the
corresponding low power modes
0Hard
Reset
RW
3 CQ10453 improvement
Disable (BCM5787,
BCM5787M, BCM5754, and
BCM5754M only)
• 1 = Enable CQ10453 improvement, meaning
to reset the L1 enter timer upon any TLP
request.
• 0 = Disable CQ10453 improvement.
Meaning to set off L1 re-enter L1 timer if
waked up by a config access. Device re-
enters to L1 link state after pre-defined time
() if device is still programmed in D3 state.
0RO
Reserved (other devices) 0 RO