Broadcom BCM5722 - Table 526: Autodetect Sgmii;Media Converter Register (Address 1 Ch, Shadow Value 11000)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 467 Transceiver Registers Document 5722-PG101-R
Programmable LED I/O Control
Setting LED GPIO Control/Status register bits [3:0] set the LED pin to disable LED output. Clearing LED GPIO Control/Status
register bits [3:0] set the LED pin to enable LED output.
AUTODETECT SGMII/MEDIA CONVERTER (PHY_ADDR = 0X1, REG_ADDR = 1CH, SHADOW
11000B)
Write Enable
During a write to this register, setting Autodetect SGMII/Media Converter register bit 15 allows writing to bits [9:0] of this
register. For reading the values of bits [9:0], perform an MDIO write with bit 15 cleared and preferred shadow values in bits
[14:10]. The next MDIO read of register address 1Ch contains the preferred Shadow register values in bits [9:0].
Shadow Register Selector
Register bits [14:10] of this register must be set to 11000 to enable read/write to the Autodetect SGMII/Media Converter
address 1Ch.
SerDes Resolution Fault
Bit 9 of the Auto-Detect SGMII/Media Converter register indicates there is a selected field mismatch on bit 0 of the base page
word. Otherwise, it reads a 0.
SGMII/Media Converter Autodetect Mode Enable
Setting Bit 0 of the Auto-Detect SGMII/Media Converter register enable the SGMII/media converter autodetect mode.
Otherwise, it is in the normal mode.
Table 526: Autodetect SGMII/Media Converter Register (Address 1Ch, Shadow Value 11000)
Bit Field Description Init Access
15 Write Enable • 1 = Write bits [9:0].
• 0 = Read bits [9:0].
0R/W
14:10 Shadow Register
Selector
11000 = Autodetect SGMII/Media Converter register. 11000 R/W
9 SerDes Resolution
Fault
• 1 = Selected field mismatch.
• 0 = No mismatch or SGMII/media converter autodetect
mode is disabled.
0RO
8:1 Reserved Write as 00h, ignore when read. 00h RO
0 SGMII/Media Converter
Autodetect Mode
Enable
• 1 = Enable SGMII/media converter autodetect mode.
• 0 = Normal operation.
INTF_SEL[3]
AND RXCDLY
R/W