Broadcom BCM5722 - Table 81: WOL Mode Clock Inputs; Table 82: Magic Packet Detection Logic Enable

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Programmer’s Guide BCM5722

10/15/07

Broadcom Corporation

Document 5722-PG101-R Wake on LAN Mode/Low-Power Page 166

Power Management

The clocking inputs need to be modified for WOL mode (see Table 81). The RX CPU is not required during WOL operation,

so its clock can be disabled. The MAC has an internal phase-locked loop that clocks internal logic at 133 MHz. Software

must select an alternate clocking source and then disable this PLL.

The settings shown in Table 82 enable Magic Packet detection logic in the MAC. These setting also enable the MAC to as-

sert PME on the PCI bus. The RX MAC should maintain the multicast and broadcast settings that were previously configured

by the NOS. The Microsoft power management specification states:

“Only a frame that passes the device’s MAC, broadcast, or multicast address filter and matches on the previously loaded

sample patterns will cause the wake-up signal to be asserted.”

The ACPI_Power-on bit needs to be set for pattern match, but not for Magic Packet recognition. The Magic Packet detection

mechanism is separate from the pattern match mechanism. Host software may configure WOL using four filter permutations:

• Pattern match WOL disabled. Magic Packet disabled.

• Pattern match WOL enabled. Magic Packet disabled.

• Pattern match WOL disabled. Magic Packet enabled.

• Pattern match WOL enabled. Magic Packet enabled.

Table 81: WOL Mode Clock Inputs

PCI Clock_Control RX RISC_Clock_Disable Set the bit to 1

PCI Clock_Control Select_Alternate_Clock Set the bit to 1

PCI Clock_Control PLL133 Set the bit to 1

Table 82: Magic Packet Detection Logic Enable

PCI Power_Management_Control/Status PME_Enable Enable

PCI Power_Management_Control/Status Power_State 0x03

Ethernet_MAC_Mode ACPI_Power-On See above

Ethernet_MAC_Mode Magic_Packet_Detection See above