Broadcom BCM5722 - Table 385: Auxiliary Smbus Slave Address;Control Register (Offset 0 X6 C50); Table 386: Auxiliary Smbus Slave Status Register (Offset 0 X6 C54)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 365 ASF Support Registers Document 5722-PG101-R
AUXILIARY SMBUS SLAVE ADDRESS/CONTROL REGISTER (OFFSET 0X6C50)
AUXILIARY SMBUS SLAVE STATUS REGISTER (OFFSET 0X6C54)
Table 385: Auxiliary SMBus Slave Address/Control Register (Offset 0x6C50)
Bit Field Description Init Access
31:8 Reserved – 0 R/W
7:1 SMBus Slave Address Only meaningful if AV flag is set. User also needs to
program bit 0 of register 0x6C64 AV_REG to mark address
valid based on SMBus 2.0 spec.
0R/W
0 Slave Enable
• 0 = Disable
• 1 = Enable Slave Interface. (This bit must also be set for
ARP offload)
0R/W
Table 386: Auxiliary SMBus Slave Status Register (Offset 0x6C54)
Bit Field Description Init Access
31:3 Reserved – 0 R/W
2 Slave Read Requested
• 0 = SMBus Attention not caused by slave.
• 1 = Source of SMBus attention is slave read cycle that
matched the SMB Slave address.
This bit is only set by hardware and can be reset by writing
a 1 to this position. Slave interface stretches the clock until
this bit is cleared.
Read request for ARP will not trigger this bit. ARP hardware
will supply read data in wire speed.
0R/W
1 Slave Cycle Complete
• 0 = SMBus Attention not caused by slave.
• 1 = Source of SMBus attention is completion of a slave
cycle that matched the SMB Slave address.
This bit is only set by hardware and can be reset by writing
a 1 to this position.
Completion for ARP will not trigger this bit. ARP Status
register contains that information.
0R/W
0Slave Busy
• 0 = SMBus Controller slave interface is not processing
data.
• 1 = Indicates that the SMBus Controller slave interface is
in the process of receiving data. None of the other SMBus
Slave registers should be accessed if this bit is set.
Note: This bit is also set during ARP process.
0RO