Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Ethernet MAC Control Registers Page 246
ETHERNET MAC STATUS REGISTER (OFFSET 0X404)
Table 191: Ethernet MAC Status Register (Offset 0x404)
Bit Field Description Init Access
31:29 Reserved Always 0. 0 RO
28 Interesting Packet PME
Attention
When this bit is set, the WOL signal is asserted when
an interesting packet is detected.
0W2C
27 TX Statistic Overrun Transmit Statistics block has overrun. Generates an
attention when enabled.
0W2C
26 RX Statistic Overrun Receive Statistics block has overrun. Generates an
attention when enabled.
0W2C
25 ODI Error Output Data Interface block has an overrun or
underrun. Will generate attention when enabled. Clear
this attention using the Transmit Status Register.
0RO
24 AP Error Auto-polling interface needs service. Generates an
attention when enabled. Clear this attention using the
Auto-polling Status Register.
0RO
23 MI Interrupt Management Interface is signalling an interrupt.
Generates an attention when enabled.
0RO
22 MI Completion Management Interface transaction has completed.
Generates an attention when enabled.
0W2C
21-13 Reserved – 0 RO
12 Link State Changed Set when the link state has changed. Generates an
attention when enabled by bit 12 of the Ethernet MAC
Event Enable register (see “Ethernet MAC Event
Enable Register (Offset 0x408)” on page 247). Clear
this attention by writing 1 to Sync Changed (bit 4) and
Config changed (bit 3).
0W2C
11-1 Reserved – 0 RO
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