BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 335 General Control Registers Document 5722-PG101-R
MISCELLANEOUS CONFIGURATION REGISTER (OFFSET 0X6804)
The Miscellaneous Configuration register is used as an extension to the Miscellaneous Local Control register (see
“Miscellaneous Local Control Register (Offset 0x6808)” on page 336). There are several fields used to control several small
counters associated with the free-running 32-bit timer inside the device. The prescale function is performed on the clock prior
to advancing the Timer register (see “Timer Register (Offset 0x680C)” on page 337) to provide a resolution as close as
possible to 1 µs.
Table 343: Miscellaneous Configuration Register (Offset 0x6804)
Bit Field Description Init Access
31:30 Reserved – 0 RO
29 Disable GRC Reset on PCIe
Block
Setting this bit will prevent PCIe link training during a GRC
reset.
0R/W
28 Wire Speed Enable
(BCM5787, BCM5787M,
BCM5754, and BCM5754M
only)
When this bit is set, wire speed detection is enabled. 1 R/W
BOND ID 5 (BCM5722,
BCM5755, BCM5755M,
BCM5756M, BCM5757 only)
1 = Super IDDQ Mode Disable ID5 RO
27 Wire Speed Timer Disable
(BCM5787, BCM5787M,
BCM5754, and BCM5754M
only)
When this bit is set, the wire speed timer is disabled. 0 R/W
BOND ID 4 (BCM5722,
BCM5755, BCM5755M,
BCM5756M, BCM5757 only)
– ID4 RO
26 GPHY Power Down Override When this bit is set, the GPHY will be left powered up when
in the D0 uninitialized state.
• In A1, this bit can only be cleared by a hard reset. A GRC
or PCI reset has no effect.
• In A0, this bit can be cleared by hard-reset, GRC reset,
or PCI reset.
Note: See “Revision Levels” on page 8.
0R/W
Reserved (BCM5906 only) – 0 R/W
25 DDQ_DLL Enable Disable When this bit is set, the handshake with the GPHY to power
down the DLL is disabled. The IDDQ_DLL_Enable will
always be 1.
0R/W
Reserved (BCM5906 only) – 0 R/W
24 RAM Power Down When this bit is set, all of the RAMs are powered down. 0 R/W
23 VREG Standby Current Mode When this bit is set, both vreg1 and vreg2 will be put into
standby current mode (which consumes < 1 mA).
0R/W
22 BIAS IDDQ When this bit is set, the BIAS will be powered down. 0 R/W
Reserved (BCM5906 only) – 0 R/W
21 PHY IDDQ When this bit is set, the PHY will be powered down. 0 R/W
20 Device Power Down Setting this bit will power down the device (power
consumption is ~20 mW). This bit is cleared by PCI reset.
0R/W
19 Vmain_prsnt (BCM5906 only) Current status of vmain_prsnt signal 0 RO
Reserved (all others) –
18:17 Reserved – 0 RO
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