Broadcom BCM5722 - MAC RX MBUF Low Watermark Register (Offset 0 X4414); MBUF High Watermark Register (Offset 0 X4418); RX RISC MBUF Cluster Allocation Request Register (Offset 0 X441 C); Table 302: RX RISC MBUF Allocation Request Register (Offset 0 X441 C)

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Programmer’s Guide BCM5722

10/15/07

Broadcom Corporation

Document 5722-PG101-R Buffer Manager Control Registers Page 308

MAC RX MBUF LOW WATERMARK REGISTER (OFFSET 0X4414)

This 32-bit register indicates the number of free MBUFs that must be available for the RX MAC to accept a frame. If the free

MBUF count drops below this mark, it must go above the high watermark to resume normal operation.

MBUF HIGH WATERMARK REGISTER (OFFSET 0X4418)

This 32-bit register indicates the number of free MBUFs that must be available before normal operation is restored to the

Read DMA Engine and/or the RX MAC.

RX RISC MBUF CLUSTER ALLOCATION REQUEST REGISTER (OFFSET 0X441C)

The RX RISC MBUF Cluster Allocation Request register contains two fields:

• A requested size field which can be up to 64 KB long

• An allocation bit

The allocation bit is used to control the access to the response register. Use this register to set the size and allocation bit

and then poll the register until the allocation bit is cleared. When the allocation bit is cleared, it is safe to read from the RX

RISC MBUF Cluster Allocation Response register.

Note: For the BCM5906 device, the recommended value for 0x4414 is 0x4.

Note: When the MAC RX MBUF Low watermark has been reached, the RX MAC continues to accept incoming

frames as configured by the “Low Watermark Maximum Receive Frames Register (Offset 0x504)” on page 258.

If these additional incoming frames cause the MBUF free count to drop to 0, the Buffer Manager may stall and

require a controller reset to recover.

Note: For the BCM5906 device, the recommended value for 0x4418 is 0x10.

Note: This register is not applicable to the BCM5906 device.

Table 302: RX RISC MBUF Allocation Request Register (Offset 0x441C)

Bit Field Description Init Access

31 Allocation Bit Set this bit to 1 to request for the MBUF.

When this bit is read as 0, then read the MBUF Allocation

Response register (see “RX RISC MBUF Allocation

Response Register (Offset 0x4420)” on page 309) for the

TXMBUF pointer.

0R/W

30:0 Reserved – 0x0 RO