BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 405 PCIe Registers Document 5722-PG101-R
PHY MODE REGISTER (OFFSET 0X7E00)
PHY/LINK STATUS REGISTER (OFFSET 0X7E04)
2 dASPM10usTimer Disable ASPM 10us Timer before next ASPM
L1 request after naked ASPM L1 request. This
is a PCIe1.1 requirement. Assertion of disable
will go back to 1.0a version.
0 Chip
(hard +
soft)
RW
1 dFFU_EL1 Disable fast flow control update on exit of L1.
This is a PCIe1.1 requirement. If disable is
asserted, will go back to 1.0a version.
0 Chip
(hard +
soft)
RW
0 dFlowCtlUpdate1_1 Disable PCIe 1.1 flow control update rate of
34us. If disable is asserted, will go back to the
1.0a version with 44us update rate.
0 Chip
(hard +
soft)
RW
Table 461: PHY Mode Register (Offset 0x7E00)
Bit Field Description Init Access
31:2 Reserved Write as 0, ignore when read. 0 RO
1 Link disable Disable the logical PHY layer functions. 0 R/W
0 Soft reset Softreset to the phylogical block. This bit will be self-
cleared after four clock cycles.
0R/W
Table 462: PHY/Link Status Register (Offset 0x7E04)
Bit Field Description Init Access
31:8 Reserved – 0 RO
7 Link partner request
loopback
Link partner requested remote loopback mode during
training process.
0RO
6 Link partner disable
scrambler
The link partner disabled the scrambler during training
process.
0RO
5 Extended Synch Extended synchronization from PCI configuration
register. If set, 4K FTS ordered sets must be sent during
link recovery.
0RO
4 Polarity inverted Lane polarity is inverted. 0 RO
3 Link Up The link training process is completed and link is ready
for use.
0RO
2 Link training The link is in the training process. 0 RO
1 Receive data valid Symbol synchronization is achieved and receive data is
valid
0RO
0–
Table 460: Link PCIe 1.1 Control Register (0x7D54) (Cont.)
Bit Field Description Init Reset Access
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