Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Transceiver Registers Page 414
TRANSCEIVER REGISTERS
This section describes the MII registers of the integrated 10/100/1000T PHY transceivers. The access to the transceiver
registers is provided indirectly through the MII Communication Register (see “MI Communication Register (Offset 0x44C)”
on page 251) of the MAC. The transceiver registers are accessed with the PHY_Addr bit of the MII Communication Register
set to 0x1. The integrated transceiver contains the set of registers shown in Table 477.
R/W = Read/Write; RO = Read only
LH = Latched High; LL = Latched Low
H = Fixed High; L = Fixed Low
SC = Self Clear
Note: The 10/100/1000T PHY transceiver is not applicable to BCM5906 as it is a 10/100 PHY. Refer to
“Transceiver Registers (BCM5906/BCM5906M)” on page 481 for information on those devices.
Table 477: Transceiver Register Map
Reg_Addr Register
00h MII Control register
01h MII Status register
02h PHY Identifier
03h PHY Identifier
04h Auto-negotiation Advertisement
05h Auto-negotiation Link Partner BASE Page Ability
06h Auto-negotiation Expansion register
07h Auto-negotiation Next Page Transmit
08h Auto-negotiation Link Partner Received Next Page
09h 1000BASE-T Control register
0Ah 1000BASE-T Status register
0B-0Eh Reserved*
0Fh IEEE Extended Status register
10h PHY Extended Control register
11h PHY Extended Status register
12h Receive Error Counter
13h False Carrier Sense Counter
14h Receiver NOT_OK Counters
15h-17h Reserved*
18h Auxiliary Control register
19h Auxiliary Status Summary register
1Ah Interrupt Status register
1Bh Interrupt Mask register
1Ch Reserved*
1D-1Fh Test Registers
* Reserved registers should never be read or written.
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