Broadcom BCM5722 - Registers; Table 91: Interrupt-Related Registers

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Host Coalescing Page 178
REGISTERS
The BCM5722 Ethernet controller supports a variety of registers that affect status block updates and interrupt generation
(see Table 91).
Table 91: Interrupt-Related Registers
Register Cross Reference
Miscellaneous Host Control register.
The two bits of this register that are related to interrupts are:
• Mask PCI Interrupt Output (aka Mask Interrupt) bit
• Clear Interrupt INTA bit
“Miscellaneous Host Control Register (Offset 0x68)” on
page 204.
Miscellaneous Local Control register.
The two bits of this register that are related to interrupts are:
• Set Interrupt bit
• Clear Interrupt bit
“Miscellaneous Local Control Register (Offset 0x6808)” on
page 336.
Interrupt Mailbox 0 register “Interrupt Mailbox 0 Register (Offset 0x200–0x207)” on
page 238 for host standard and flat modes and “Interrupt
Mailbox 0 Register (Offset 0x5800–0x5807)” on page 325 for
indirect mode.
Receive Coalescing Ticks register “Receive Coalescing Ticks Registers (Offset 0x3C08)” on
page 295.
Send Coalescing Ticks register “Send Max Coalesced BD Count (Offset 0x3C14)” on
page 296.
Receive Max Coalesced BD Count register “Receive Max Coalesced BD Count (Offset 0x3C10)” on
page 296.
Send Max Coalesced BD Count register “Send Max Coalesced BD Count (Offset 0x3C14)” on
page 296.
Receive Max Coalesced BD Count During Interrupt register “Receive Max Coalesced BD Count During Interrupt (Offset
0x3C20)” on page 297.
Send Max Coalesced BD Count During Interrupt register .“Send Max Coalesced BD Count During Interrupt (Offset
0x3C24)” on page 297