Broadcom BCM5722 - Table 319: Virtual CPU Registers; Table 320: VCPU Status Register Fields (Offset 0 X5100); VCPU Status Register (Offset 0 X5100); Virtual CPU Registers (BCM5906 Only)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 321 Virtual CPU Registers (BCM5906 Only) Document 5722-PG101-R
VIRTUAL CPU REGISTERS (BCM5906 ONLY)
The following Virtual CPU registers are exposed to host software to provide a mechanism to control the bootcode execution
and to pick up configuration data stored inside the EEPROM. The information in this section is not intended to provide a
comprehensive understanding of the VCPU architecture.
VCPU STATUS REGISTER (OFFSET 0X5100)
This register controls the operation of the VCPU and provides the monitoring of the VCPU activities.
Table 319: Virtual CPU Registers
Offset Register
0x5100–0x5103 VCPU Status Register
0x5104–0x5107 Device Configuration Shadow Register
0x5108–0x510b VCPU Holding Register
0x510c–0x510f VCPU Data Register
0x5110–0x5113 VCPU Debug Register
0x5114–0x5117 VCPU Config Shadow 1 Register
0x5118–0x511B VCPU Config Shadow 2 Register
0x511C–0x53ff Reserved
Table 320: VCPU Status Register Fields (Offset 0x5100)
Bit Field Description Init Access
31 Invalid Signature When set to ‘1’, indicates that an invalid signature is fetched from
EEPROM. The VCPU stops execution until a reset is issued.
0RO
30 Parity Error When set to ‘1’, indicates that an instruction with parity error is
fetched from EEPROM or internal ROM. The VCPU stops stop
execution until a reset is issued.
0RO
29 Illegal Opcode When set to ‘1’, indicates that an illegal op-code is fetched from
EEPROM or internal ROM. The VCPU stops execution until a
reset is issued.
0RO
28 Idle Instruction When set to ‘1’, indicates that an Idle instruction is fetched from
EEPROM or internal ROM. The VCPU stops execution until a
reset is issued.
0RO
27 Driver Reset When set to ‘1’, the driver reset booting procedure is different
than the other resets. The bootcode checks this bit to decide
which procedure to choose. This bit is cleared on a hard reset.
Note: The driver needs to set this bit to “1” before issuing a GRC
or VCPU reset. Combining with bit 26, the driver can
communicate with the Broadcom device on the reset/init
sequence.
0RW
26 Init Done Indicates to the host that the VCPU has finished the initialization
and the host can start the driver loading.
0R/W