BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 215 PCIe Capabilities Document 5722-PG101-R
PCIE CAPABILITIES
PCIe devices include new status and control registers that are located in the Capabilities List in the device's PCI
Configuration Space. These PCIe capabilities registers start at offset 0xD0 of PCI Configuration Space.
PCIE CAPABILITY LIST REGISTER (OFFSET 0XD0)
This eight-bit register identifies this item in the Capabilities List as a PCIe register set. This value is hardwired to 0x10 to
indicate the PCIe capabilities set.
PCIE NEXT CAPABILITIES POINTER REGISTER (OFFSET 0XD1)
This eight-bit register points to the next item in the capabilities List.
PCIE CAPABILITIES REGISTER (OFFSET 0XD2)
Table 141: PCIe Capability ID Register (Offset 0xD0)
Bit Field Description Init Access
7:0 PCIe Capability ID Identifies this item as PCIe capabilities. 10h RO
Table 142: PCIe Next Capabilities Pointer Register (Offset 0xD1)
Bit Field Description Init Access
7:0 PCIe Next Capabilities Points to the next capabilities block, which is NULL,
because this is the last item in the capabilities list.
00h RO
Table 143: PCIe Capabilities Register (Offset 0xD2)
Bit Field Description Init Access
15:14 Reserved – 0 R/W
13:9 Interrupt Message
Number
This register contains the MSI Data value that is written to the MSI
destination address when any status bit in either the Slot Status
register or the Root Status register is set.
0R/W
a
a. Writable by internal processors.
8 Slot Implemented This register is hardwired to 0 because this is an endpoint device. 0 RO
7:4 Device/Port Type This register is hardwired to 0 because this is an endpoint device. 0 RO
3:0 Capability Version This register indicates the version of the PCIe Capability structure. 1 RO
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