Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R PCIe-Enhanced Capabilities Page 228
HEADER LOG REGISTER (OFFSET 0X11C–0X12B)
The Header Log Registers store the TLP header of the transaction that has incurred a failure.
VIRTUAL CHANNEL ENHANCED CAPABILITY HEADER (OFFSET 0X13C)
PORT VC CAPABILITY REGISTER (OFFSET 0X140)
PORT VC CAPABILITY REGISTER 2 (OFFSET 0X144)
PORT VC CONTROL REGISTER (OFFSET 0X148)
4:0 First Error Pointer This value indicates the bit position within the
“Uncorrectable Error Status Register (Offset 0x104)” on
page 224 corresponding to the first error detected.
0RO
Table 162: Virtual Channel Enhanced Capability Header (Offset 0x13c)
Bit Field Description Init Access
31:20 Next Capability Offset 0x160 RO
19:16 Capability Version 0x1 RO
15:0 PCIe Extended Capability ID Extended Capability ID for the Virtual Channel
Capability is 0002h
0x0002 RO
Table 163: Port VC Capability Register (Offset 0x140)
Bit Field Description Init Access
11:10 Port Arbitration Table Entry Size Must be set to 0 for endpoint devices 0x0 RO
9:8 Reference Clock Must be set to 0 for endpoint devices 0x0 RO
6:4 Low Priority Extended VC Count Only default VC is supported 0x0 RO
2:0 Extended VC Count Only default VC is supported 0x0 RO
Table 164: Port VC Capability Register 2 (Offset 0x144)
Bit Field Description Init Access
31:24 VC Arbitration Table Offset Table not present. 0x00 RO
7:0 VC Arbitration Capability Field not valid when Low Priority Extended VC
Count = 0.
0x00 RO
Table 165: Port VC Control Register (Offset 0x148)
Bit Field Description Init Access
3:1 VC Arbitration Select Not supported 0x0 RO
0 Load VC Arbitration Table Not supported 0 RO
Table 161: Advanced Error Capabilities and Control Register (Offset 0x118) (Cont.)
Bit Field Description Init Access
To Next Page
Loading...