Broadcom BCM5722 - Table 490: PHY Extended Control Register (Phy_Addr = 0 X1, Reg_Addr = 10 H)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Transceiver Registers Page 428
PHY EXTENDED CONTROL REGISTER (PHY_ADDR = 0X1, REG_ADDR = 10H)
12 1000BASE-T Half-
Duplex Capability
The BCM5722 Ethernet controller is capable of
1000BASE-T half-duplex operation, and returns a 1 when
bit 12 of the IEEE extended Status Register is read.
• 1 = 1000BASE-T half-duplex capable.
• 0 = Not 1000BASE-T half-duplex capable.
1RO
H
11:0 Reserved Write as 0, ignore on read. 0 RO
Table 490: PHY Extended Control Register (PHY_Addr = 0x1, Reg_Addr = 10h)
Bit Field Description Init Access
15 MAC/PHY Interface
Mode
The MAC/PHY interface is GMII.
• 1 = TBI (10-bit Interface).
• 0 = GMII.
0R/W
14 Disable Automatic MDI
Crossover
The automatic MDI crossover function can be disabled by
writing a 1 to bit 14 of the PHY Extended Control Register.
When the bit is written to 0, the BCM5722 Ethernet controller
performs the automatic MDI crossover function (see “Automatic
MDI Crossover” on page 35).
• 1 = Automatic MDI crossover disabled.
• 0 = Automatic MDI crossover enabled.
0R/W
13 Transmit Disable The transmitter can be disabled by writing a 1 to bit 13 of the
PHY Extended Control Register. The transmitter outputs (TRD
±
{0...3}) are forced into a high impedance state.
• 1 = Transmitter outputs disabled.
• 0 = Normal operation.
0R/W
12 Interrupt Disable
• 1 = Interrupt status output disabled.
• 0 = Interrupt status output enabled.
0R/W
11 Force Interrupt
• 1 = Force interrupt status to active.
• 0 = Normal operation.
0R/W
10 Bypass 4B/5B
Encoder/Decoder
The 100BASE-TX 4B/5B encoder/decoder can be bypassed by
writing a 1 to bit 10:
• 1 = Transmit and receive 5B codes over MII pins.
• 0 = Normal MII.
0R/W
9 Bypass Scrambler/
Descrambler
The 100BASE-TX stream cipher function can be disabled by
writing a 1 to bit 9 of the PHY Extended Control Register. The
stream cipher function can be re-enabled by writing a 0 to this
bit.
• 1 = Scrambler and descrambler disabled.
• 0 = Scrambler and descrambler enabled.
0R/W
8 Bypass MLT3 Encoder/
Decoder
The 100BASE-TX MLT3 encoder and decoder can be
bypassed by writing a 1 to bit 8 of the PHY Extended Control
Register. NRZ data is transmitted and received on the cable.
The MLT3 encoder can be re-enabled by writing a 0 to this bit.
• 1 = Bypass NRZI/MLT3 encoder and decoder.
• 0 = Normal operation.
0R/W
Table 489: IEEE Extended Status Register (PHY_Addr = 0x1, Reg_Addr = 0Fh) (Cont.)
Bit Field Description Init Access