Broadcom BCM5722 - Table 463: Phy;Link LTSSM Control Register (Offset 0 X7 E08); Table 464: Phy;Link Training Link Number (Offset 0 X7 E0 C); Table 465: Phy;Link Training Lane Number (Offset 0 X7 E10)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R PCIe Registers Page 406
PHY/LINK LTSSM CONTROL REGISTER (OFFSET 0X7E08)
PHY/LINK TRAINING LINK NUMBER (OFFSET 0X7E0C)
PHY/LINK TRAINING LANE NUMBER (OFFSET 0X7E10)
Table 463: PHY/Link LTSSM Control Register (Offset 0x7E08)
Bit Field Description Init Access
31:8 Reserved – 0 RO
7 DisableScramble Disable scrambling and de-scrambling. 0 R/W
6 DetectState High layer directs LTSSM to detect state if set. The bit is
cleared when LTSSM entered into detect state.
0R/W
5 PollingState High layer directs LTSSM to Polling state if set. The bit is
cleared when LTSSM entered into Polling state.
0R/W
4 ConfigState High layer directs LTSSM to configuration state if set. The
bit is cleared when LTSSM entered into configuration
state.
0R/W
3 RecovState High layer directs LTSSM to recovery state if set. The bit
is cleared when LTSSM entered into recovery state.
0R/W
2 ExtLBState High layer directs LTSSM to external loopback master
state if set. The bit is cleared when LTSSM entered into
master external loopback state.
0R/W
1 ResetState High layer directs LTSSM to hot reset state if set. The bit
is cleared when LTSSM exited out of the hot reset state.
0R/W
0 DisableState High layer directs LTSSM to disable state if set. The bit is
cleared when LTSSM entered into disable state.
0R/W
Table 464: PHY/Link Training Link Number (Offset 0x7E0C)
Bit Field Description Init Access
31:8 Reserved – 0 RO
7:0 Lane Number Lane Number within component PAD RO
Table 465: PHY/Link Training Lane Number (Offset 0x7E10)
Bit Field Description Init Access
31:8 Reserved – 0 RO
7:0 Lane Number Lane Number within link PAD RO