Broadcom BCM5722 - Table 355: RX CPU Event Enable Register (Offset 0 X684 C)-BCM5906 Only

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R General Control Registers Page 344
Table 355: RX CPU Event Enable Register (Offset 0x684C)—BCM5906 Only
Bit Field Description Init Access
31 Flash – 0 RO
30 VPD – 0 RO
29 Reserved – 0 R/W
28 ROM – 0 RO
27 HC module – 0 RO
26 Reserved – 0 RO
25 EMAC module – 0 RO
24 Memory Map Enable Bit Set by HW, cleared by SW 0 R/W
23 Reserved - – 0 R/W
22 Reserved - – 0 RO
21 Low-Priority Mail Box - – 0 RO
20 DMA - – 0 RO
19 Reserved - – 0 R/W
18 Datalink Layer - – 00 R/W
17 Physical Layer –
16:11 Reserved - – 0 R/W
10 SDC (Post TCP
segmentation) -
–0RO
9 SDI (Pre TCP segmentation)
-
–0RO
8 RDIQ FTQ – 0 RO
7:0 Reserved – 0 R/W