Broadcom BCM5722 - Figure 53: PCI Base Address Register Bits Read in Flat Mode; Table 50: PCI Registers

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 131 Configuration Space Document 5722-PG101-R
When the BCM5722 Ethernet controller is programmed in flat mode, a 32M region of memory mapped I/O needs to be made
available. The PnP BIOS/OS will probe the BAR, and scan upwards looking for the first programmable bit. Again, bits 0–3
are ignored. The mask 0xE000000 identifies the BAR bits, which are programmable. Bit 25 is the first bit encountered in the
scan upward, which is programmable. Host software will read zero values from bits 4–24. Figure 53 shows the BAR register
and the bits returned to the OS/BIOS during resource allocation.
Figure 53: PCI Base Address Register Bits Read in Flat Mode
REGISTER QUICK CROSS REFERENCE
BCM5722 Family
The BCM5722 Ethernet controller PCI registers are listed in Table 50.
Table 50: PCI Registers
Register Bit Cross Reference
PCI Command Memory_Space “Command Register (Offset 0x04)” on page 190.
PCI Command IO_Space “Command Register (Offset 0x04)” on page 190.
PCI State Flat_View “PCI State Register (Offset 0x70)” on page 206.
PCI Base Address 1 All “Base Address Register 1/2 (Offset 0x10–0x17)” on page 193.
PCI Base Address 2 All “Base Address Register 1/2 (Offset 0x10–0x17)” on page 193.
XXXX XX10 0000 0000 0000 0000 0000 0 11 0
[0
]
[2:1][3]
[31:4]
Binary Weighted Value:
0x02000000 = 2M
X's are don't cares