Broadcom BCM5722 - Figure 15: Smbus Transaction Phases; Figure 16: SMB_CLOCK Period (Master Mode)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 31 System Management Bus Document 5722-PG101-R
Figure 15: SMBus Transaction Phases
SMBus Clock
The BCM5722 Ethernet controller’s SMBus interface supports clock stretching. Slave devices may clock low to extend the
SMB_CLK signal, and the BCM5722 Ethernet controller absorbs the stretch latency. The programmer should refer to section
4.3.3 of the SMBus 2.0 manual for further details on this technology. The BCM5722 Ethernet controller maintains a minimum
compliant frequency of 10 KHz when clock is low extending.
The BCM5722 Ethernet controller’s clock period (master mode) is 11 µs—a 90.9-KHz frequency. The SMB_CLK signal is
driven low T
Low
for 5 µs. The BCM5722 Ethernet controller floats the SMB_CLK high T
High
for a maximum of 6 µs before the
SMB_CLK is driven low again. The low and high times are not guaranteed symmetric, since the rise may vary due to external
pull-up resistors or current sources. The rise time T
R
on SMB_CLK will vary from 300 ns to 1 µs. The fall time T
F
is roughly
500 ns, but also may vary. See Figure 16.
Figure 16: SMB_CLOCK Period (Master Mode)
EVENTS
The SMB Attention bit and the five timeout bits in the ASF Control register are all ORed together to form a single ASF_ATTN
signal. Depending on the value of the ASF Attention Location field, this signal may then be mapped into one of several bit
positions in the RX CPU Event or TX CPU Event registers.
Start
Condition
Slave Address
Read/Write
Acknowledge
Stop
Conditio
n
1
2
3
4
5
7
02 810
18
Data Byte
Acknowledge6
20
S
MB_CLK
300 ns–1 µs
T
R
T
F
500 ns
T
High,Max
T
Low
5 µs
6 µs