BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 401 PCIe Registers Document 5722-PG101-R
RETRY BUFFER PURGED POINTER DEBUG REGISTER (OFFSET 0X7D34)
RETRY BUFFER READ/WRITE DEBUG PORT (OFFSET 0X7D38)
ERROR COUNT THRESHOLD REGISTER (OFFSET 0X7D3C)
TLP ERROR COUNTER REGISTER (OFFSET 0X7D40)
Table 452: Retry Buffer Purged Pointer Debug Register (Offset 0x7D34)
Bit Field Description Init Access
31:11 Reserved Write as 0, ignore when read. 0 RO
10:0 Retry Buffer Purged
Pointer
Starting address of next TLP to be purged from retry
buffer RAM.
0R/W
Table 453: Retry Buffer Read/Write Debug Port (Offset 0x7D38)
Bit Field Description Init Access
31:0 Retry Buffer Data Data written to this address is written into the retry buffer
RAM at the retry buffer write address. Reads to this
address will return the data stored at the retry buffer read
address in the retry buffer RAM.
–R/W
Table 454: Error Count Threshold Register (Offset 0x7D3C)
Bit Field Description Init Access
31:15 Reserved Write as 0, ignore when read. 0 RO
14:12 Bad Sequence Number
Count Threshold
Attention bits are set when error count reaches threshold.
Threshold = 2^n.
0x7 R/W
11:8 NAK Received Count
Threshold
Attention bits are set when error count reaches threshold.
Threshold = 2^n.
0xF R/W
7:4 DLLP Error Count
Threshold
Attention bits are set when error count reaches threshold.
Threshold = 2^n.
0xF R/W
3:0 TLP Error Count
Threshold
Attention bits are set when error count reaches threshold.
Threshold = 2^n.
0xF R/W
Table 455: TLP Error Counter Register (Offset 0x7D40)
Bit Field Description Init Access
31:24 Reserved Write as 0, ignore when read. 0 RO
23:16 TLP Bad Sequence
Number Counter
Counts number of TLPs with bad sequence number
received since last read. Counter freezes at max value
and will be cleared to one if event occurs simultaneously
to read.
0RO/CR
15:0 TLP Error Counter Counts number of bad TLPs received (includes bad
LCRC, bad length or bad sequence number) since last
read. Counter freezes at max value and will be cleared to
one if event occurs simultaneously to read.
0RO/CR